View CXP402_445532.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP402
CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office.
Description The CXP402 is a CMOS 4-bit single chip microcomputer which consists of 4-bit CPU, ROM, RAM, 8-bit timer, 8-bit timer/counter, 18-bit time-base timer, LCD controller/driver, digital signal processor circuit for CD player, 1-bit DAC and the like. Features * Instruction cycle 1.89s for 16.93MHz oscillation * ROM capacity 6144 x 8 bits * RAM capacity 400 x 4 bits (Including stack and display area) * LCD controller/driver (Enables to direct drive) * 8-bit timer, 8-bit timer/event counter and 18-bit time-base timer are incorporated; they are independently controllable. * Arithmetic and logical operations between the entire RAM area, I/O area and the accumulator by means of the memory mapped I/O. * Entire ROM area can be referred by the table lookup instruction. Digital Signal Processor (DSP) Block * Playback mode supporting CAV (Constant Angular Velocity) * Frame jitter free * Allows relative rotational velocity readout * Supports spindle external control * Wide capture range playback mode * Spindle rotational velocity following method * 16K RAM * EFM data demodulation * Enhanced EFM frame sync signal protection * SEC strategy-based error correction * Subcode demodulation and Sub Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry correction circuit * Servo auto sequencer * Digital audio interface output * Digital peak meter 112 pin LQFP (Plastic)
Digital Filter, DAC and Analog Low-Pass Filter Blocks * DBB (digital bass boost) function * Digital de-emphasis * Digital attenuation * Zero detection function * 8Fs oversampling digital filter * S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB * THD + N: 0.007% or less (master clock: 384Fs, typ.) * Rejection band attenuation: -60dB or more * 112-pin plastic LQFP * Piggyback package (CXP401Z) available Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98924-PS
Block Diagram
COM3
SEG0
VLC2
VLC3
SEG1
VLC1
SCOR
XRSTO
SBSO
C4M
PCO
SEG2
COM0
EMPH
CNIN
MDP
VCTL
SEG3
COM1
GFS
SEIN
MDS
V16M
COM2
CLKO
MON
VCKI
AVSS
CLTV
AVDD
BIAS RF
XLTO
LOCK
VPCO2
FILO
FOK
DATO
EXCK
VPCO1
85 86 87 88 89 90 91 92 95 94 93 53 51 30 31 40 3 4 1 5 2 54 55 11 8 10 9 49 13 12 14 15 16 17 18 19 20 21 22 24 23 25 26
LCD Controller/Driver Servo Auto Sequencer PORT I/F INT PY0 PY1 PY2 PY3 EFM Demodulator SCOR EMPHI CPU I/F Digital CLV Digital PLL Asymmetry Collector 52 WFCK 38 GTOP 39 XPCK 41 RFCK 42 C2PO 45 XROF 48 MNT0 D/A I/F 47 MNT1 46 MNT3 50 DOUT 28 TEST0 27 TEST1 EPROM Collector 56 DTEST 57 CTEST 72 VDD Test Circuit 1-bit DAC Digital Filter RST 71 VSS 44 VDD 43 VSS 7 6 OSC VDD VSS Analog Out SQCK SQSO
SEG4 84
SEG5 83
SEG6 82
SEG7 81
SEG8 80
SPC500 CPU Core
SEG9 79
SEG10 78
SEG11 77 16K RAM
SEG12 76
SEG13 75
PB1
PB2
PB3
PB0
PC0
PC1
PC2
PC3
RMC
XTAI
AIN2
AVSS
AVSS
XVSS
AIN1
AVSS
XRST
AVDD
XVDD
XTAO
AVDD
AVSS
BCKI
BCK
PCMD
AOUT2
LOUT2
LOUT1
AOUT1
PCMDI
LRCKI
LRCK
-2-
SIO I/F RMC PX0 PX3 70 29
SEG14 74
SEG15 73
ROM 6K Byte
RAM 400 x 4bit
PA0 66
PF0 PF1 PF2 PF3 PE0 PE1 PE2 PE3 PD0 PD1 PD2
ACDT RMUT LMUT DATA XLAT CLOK XRST SYSM PWMI XTSL ASYE SENS FOK GFS
PA1 67
PA2 68
PA3 69
T/C
Port
62 63 64 65 58 59 60 61
111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 37 36 35 34 33 32
FILI
ASYI
ASYO
CXP402
CXP402
Pin Configuration (Top View)
AOUT2
LOUT2
LOUT1
AOUT1
COM0
COM1
COM2
COM3
XTAO
SEG0
SEG1
SEG2
AVDD
XTAI
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
SEG3
AVDD
XVDD
AVSS
AVSS
XVSS
AVSS
AIN2
AVSS
AIN1
VLC1
NC
VLC2
VLC3
SEIN CNIN DATO XLTO CLKO VSS VDD MON MDP MDS LOCK VPCO2 VPCO1 VCKI V16M VCTL PCO FILI FILO AVSS CLTV AVDD RF BIAS ASYI ASYO TEST1 TEST0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 VDD VSS RMC PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 CTEST
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
XRSTO
PCMDI
PCMD
WFCK
EMPH
SCOR
XROF
XPCK
SBSO
C2PO
RFCK
MNT3
MNT1
MNT0
XRST
EXCK
BCKI
GFS
C4M
FOK
BCK
VSS
-3-
DTEST
LRCKI
GTOP
DOUT
LRCK
VDD
CXP402
Pin Description Symbol PA0 to PA3 I/O I/O Description (Port A) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port B) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port C) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) LCD segment signal output. (16 pins) LCD common signal output. LCD bias power supply. Bias voltage is generated, which is 1/3 the supply voltage due to the internal resistor. (3 pins) Input Input Output Output Output Output Output (tri-state) Output Output (tri-state) Input Output Input SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Serial clock output to SSP. Spindle motor ON/OFF control output. Spindle motor servo control. (2 pins) Lock signal output. GFS is sampled at 460Hz and; when GFS is high, this pin outputs a high signal. If GFS is low eight convective samples, this pin outputs low. Wide-band EFM PLL charge pump output. (2 pins) Wide-band EFM PLL VCO2 oscillation input. Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL VCO2 control voltage input.
PB0 to PB3
I/O
PC0 to PC3 SEG0 to SEG15 COM0 to COM3 VLC1 to VLC3 SEIN CNIN DATO XLTO CLKO MON MDP MDS LOCK VPCO1 VPCO2 VCKI V16M VCTL PCO FILI FILO CLTV RF BIAS ASYI ASYO XRST
I/O Output Output
Output (tri-state) Master PLL charge pump output. Input Master PLL filter input.
Output (Analog) Master PLL filter output. Input Input Input Input Output Input Master VCO control voltage input. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM output. (full swing) System reset input. Active at low. -4-
CXP402
Symbol XRSTO FOK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO EXCK AOUT1 AIN1 LOUT1 AOUT2 AIN2 LOUT2 RMC XTAI XTAO NC
I/O Output Input Output Input Output Input Output Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input
Description Reset signal output. Active at low. Focus OK input. Used for SENS output and servo auto sequencer. D/A interface LR clock output. (f = Fs) LR clock input. D/A interface serial data output. D/A interface serial data input. D/A interface bit clock output. D/A interface bit clock input. GTOP output. XPLCK output. GFS output. RFCK output. C2PO output. XRAOF output. MNT3 output. MNT1 output. MNT0 output. 1/4 frequency division output of the oscillation input. (4.2336MHz for 16.3944MHz) Digital Out output. De-emphasis ON/OFF output. High is output for ON; low is output for OFF. WFCK output. Subcode sync detection output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial data output. SBSO serial clock input.
Output (Analog) Lch analog output. Input (Analog) Output Lch operational amplifier input. Lch LINE output.
Output (Analog) Rch analog output. Input (Analog) Output Input Input Rch operational amplifier Rch LINE output. Remote control receiver circuit input. Connect a crystal for system clock oscillation. When the clock is supplied externally, input it to the XTAI pin and leave the XTAO pin open. No connected. -5-
CXP402
Symbol VDD VSS AVDD AVSS XVDD XVSS TEST1 TEST0 DTEST CTEST Input Input Input Input
I/O Positive power supply. GND.
Description
Positive power supply for analog circuit. GND for analog circuit. Positive power supply for oscillation circuit. GND for oscillation circuit.
Test for LSI. Connect to GND for normal operation.
Notes * Power supply pins AVDD, AVss, XVDD, XVss, VDD and Vss should process all the pins. * PCMD is the MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s (at normal speed). * C2PO represents the data error status. * XRAOF is generated when the 16K RAM exceeds the 4F jitter margin.
-6-
CXP402
Input/Output Circuit Formats for Pins Pin Port A Port B
Ports A, B data
Circuit format
When reset
PA0 to PA3 PB0 to PB3
Ports A, B I/O direction Input protection circuit
Hi-Z
IP
Data bus RD (Ports A, B)
8 pins Port C
Pull-up transistor approx. 50k
Port C data
PC0 to PC3
Port C I/O direction
Hi-Z
IP Data bus RD (Port C)
4 pins
Pull-up transistor approx. 50k
RMC XRST SEIN CNIN VCKI FOK LRCKI PCMDI BCKI EXCK 10 pins
Schmitt input IP Internal circuit
Hi-Z
EMPHI is not Schmitt input.
-7-
CXP402
Pin
Circuit format
When reset
VCH
SEG0 to SEG15 VDD level
VCL
16 pins
VDD
COM0 COM1 COM2 COM3
VLC1
VDD level
VLC2
4 pins
VLC3
VLC1 VLC2 VLC3
IP Internal resistor approx. 20k
VLC1 = 3/4VDD VLC2 = 2/4VDD VLC3 = 1/4VDD (when pins left open)
3 pins
XVDD
XVDD XTAI XTAO XVSS
XTAI
Oscillation
XVSS
4 pins
XTAO
-8-
CXP402
Pin
Circuit format
When reset
PCO MDP VPCO1 VPCO2 4 pins
--
MDS
MDS
--
Output enable
1 pin
VCTL FILI CLTV RF BIAS ASYI 6 pins
IP Poly resistor
--
AIN1 AIN2
IP
--
2 pins
AOUT1 AOUT2 LOUT1 LOUT2 4 pins
--
-9-
CXP402
Pin DATO XLTO CLKO LOCK MON V16M FILO ASYO XRSTO LRCK PCMD BCK GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO 27 pins
Circuit format
When reset
--
- 10 -
CXP402
Absolute Maximum Ratings Item Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VLC1, VLC2, VLC3 VIN VOUT IOH IOH IOL IOL Topr Tstg PD Symbol Ratings -0.3 to +7.01 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +7.02 -5 -70 15 100 -20 to +75 -40 to +125 600 Unit V V V V mA mA mA mA C C mW
(Vss = 0V reference) Remarks
Output pin (value per pin) Total of output pins Output pin (value per pin) Total of output pins
1 The potential difference between analog power supplies AVDD, AVss, the oscillation power supplies XVDD, XVss and VDD, Vss should be within 0.3V. 2 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operation Conditions Item Supply voltage LCD bias voltage Symbol VDD VLC1, VLC2, VLC3 VIH VIHS VIL VILS Analog input voltage Operating temperature VIA Topr Min. 3.4 VSS 0.7VDD 0.8VDD 0 0 0 -20 Max. 5.25 VDD VDD VDD 0.3VDD 0.2VDD VDD +75 Unit V V V V V V V C Hysteresis input2 3 Hysteresis input2 (Vss = 0V reference) Remarks Operation guaranteed range Liquid crystal power supply range1
High level input voltage
Low level input voltage
1 The optimal value depends on the characteristics of the used LCD element. Also, the LCD bias voltage is biased to 1/3 the supply voltage by the resistor of approximately 20k in the LSI. 2 RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, PCMDI pins 3 CLTV, FILI, RF, VCTL, AIN1, AIN2, BAIS, ASYI pins
- 11 -
CXP402
Electrical Characteristics DC characteristics Item Symbol PA, PB High level output voltage VOH BCKI, C2PO, SBSO, DATO, XLTO, CLKO, PA (VOL only), PB (VOL only), PC, MON, MDS, LOCK, LRCK, PCMD, BCK, GTOP, GFS, RFCK, XROF, MNT3, MNT1, MNT0, DOUT, WFCK, SCOR, MDP, VPCO2, VPCO1, PCO, V16M, EMPH, XPCK, ASYO, C4M, XRSTO, LRCK, PCMD XTAI PA to PC PCMDI, RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, VDD = 5.25V LRCKI, BCKI, VI = 0, 5.25V CLTV, FILI, RF, VCTL, AIN1, AIN2, MDP, MDS, VPCO1, VPCO2 VLC1, VLC2, VLC3 COM0 to COM3 SEG0 to SEG15 VDD = 5V, VLC1, VLC2, VLC3 pins left open VDD = 5.0V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V VDD = 5.25V 16.93MHz self-excited oscillation operation All output pins left open 7 3 5 Pins (Topr = -20 to +75C, VSS = AVSS = XVSS = 0V reference) Conditions VDD = 4.75V, IOH = -0.1mA VDD = 4.75V, IOH = -2.0mA VDD = 4.75V, IOH = -0.28mA VDD = 4.75V, IOL = 0.36mA VDD = 4.75V, IOL = 6.0mA VDD = 4.75V, IOL = 9.0mA VDD = 5.25V, VIH = 5.25V VDD = 5.25V, VIL = 0.4V 0.2 -0.2 -0.06 Min. 4.25 4.25 4.25 0.4 0.4 0.6 30 -30 -0.2 Typ. Max. Unit V V V V V V A A mA
Low level output voltage
VOL
IIH Input current IILE IIL
High-impedance I/O leak current
IIZ
FILO
5
A
LCD bias voltage resistance Common output impedance Segment output impedance
RB RCOM RSEG
30 5 15
k k k
Supply current
IDD
VDD, AVDD
37
80
mA
Input capacity
CIN
Pins other than VLC1 to VLC3, COM0 to COM3, SEG0 to SEG15, PA to PC, VDD, VSS, AVDD, AVSS, XVDD, XVSS
Clock 1MHz 0V for no-measured pins
10
20
pF
- 12 -
CXP402
AC Characteristics 1. XTAI pin (1) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 15 Typ. 16.93 Max. 20 Unit MHz
(2) When inputting pulses to XTAI pin (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns
tWHX tWLX tCK
VIHX VILX
tR, tF
tCK tWHX tWLX VIHX VIHX x 0.9
XTAI
VDD/2
VIHX x 0.1 VILX tR tF
(3) When inputting sine waves to XTAI pin via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit
VDD + 0.3 Vp-p
- 13 -
CXP402
2. CNIN, EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK frequency EXCK pulse width Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750
1/fCK tWCK CLK tWCK
Unit MHz ns ns ns ns ns MHz ns
tWCK tSU tH tD tWL
fT fWT
DATA XLT
tSU
tH tD tWL
EXCK CNIN tWT 1/fT SUBQ tSU tH tWT
3. BCKI, LRCKI, PCMDI pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time Symbol Conditions Min. 94 18 18 18
tW (BCKI) tW (BCKI)
Typ.
Max.
Unit ns ns ns ns
tW tSU tH tSU
BCKI
VDD/2 tSU tH (PCMDI) (PCMDI)
VDD/2
PCMDI tSU (LRCKI)
LRCKI
- 14 -
CXP402
1-bit DAC, LPF Blocks Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25C) Item Total harmonic distortion Signal-tonoise ratio Symbol THD Conditions 1kHz, 0dB data Crystal 384Fs 768Fs 384Fs 768Fs 96 96 Min. Typ. 0.0050 0.0045 100 100 Max. 0.0070 0.0065 dB Unit %
S/N
1kHz, 0dB data (A-filter)
Fs = 44.1kHz. The total harmonic distortion and signal-to-noise ratio are measured by the circuits shown below.
12k AOUT1 (2) 680p 12k AIN1 (2) 150p LOUT1 (2) 22 100k Audio Analyzer 12k SHIBASOKU (AM51A)
LPF external circuit diagram
768Fs/384Fs
Rch DATA TEST DISC RF CXP402 Lch
A Audio Analyzer
B
Block diagram of analog characteristics measurement
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage Load resistance Symbol VOUT RL 8 Min. Typ. 1.23 Max. Unit Vrms k Applicable pins 1 1
When a sine wave of 1kHz, 0dB is output. Applicable pins 1 LOUT1, LOUT2 - 15 -
CXP402
Package Outline
Unit: mm
112PIN LQFP(PLASTIC)
22.0 0.2 20.0 0.1 84 85 57 56 1.7MAX 1.4 0.1 S 0.1 S
B
A 112 1 28 0.65 0.32 0.05 0.13 M S 29
0.1 0.05
0.6 0.15
0.32 0.05
0 -- 10 DETAIL A
(0.5)
DETAIL B
(0.125)
0.25
(0.3)
0.145 0.03
(21.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-112P-L01 LQFP112-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g
- 16 -

▲Up To Search▲

Price & Availability of CXP402

	To Download CXP402 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .